Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. There have been several generations of the ARM design.

It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products. develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍-‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate different components such as memory, interfaces, and radios. Up to 32 × 64-bit registers, SIMD/floating-point (optional)ģ2-bit, except Thumb extension uses mixed 16- and 32-bit instructions.īi (little as default) in ARMv3 and aboveġ5 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)ĪRM (stylised in lowercase as arm, previously an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Thumb-2, Neon, Jazelle, DSP, Saturated, FPv4-SP, FPv5, Heliumġ5 × 32-bit integer registers, including R14 (link register), but not R15 (PC) SVE, SVE2, AES, SHA, TME All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4 obsolete: Jazelleģ2 × 128-bit registers for scalar 32- and 64-bit FP or SIMD FP or integer or cryptographyĪRMv8-R, ARMv8-M, ARMv8.1-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-Mģ2-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.

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